The present invention relates to a semiconductor device including a gate electrode which includes a polysilicon film and a method for fabricating the same, and more particularly relates to a measure for improving properties of a gate electrode.
In recent years, it has been required to improve the performance of semiconductor devices and, more specifically, MIS transistors (MISFETs) and also to reduce the power consumption thereof. To achieve improvement of performance and reduction in power consumption for semiconductor devices, reduction in OFF leakage current and suppression of the short channel effect are effective. Thus, semiconductor devices having a dual gate structure in which respective gate electrodes of an n-channel MISFET and a p-channel MISFET contain impurities (dopants) of different conductive types to each other, respectively, have been adopted (e.g., see Reference 1 (Japanese Laid-Open Publication No. 6-275788)).
FIGS. 7A through 7F and FIGS. 8A through 8E are cross-sectional views illustrating respective steps for fabricating a known semiconductor device having a dual gate structure.
First, in the process step of FIG. 7A, an isolation region 102 for dividing a surface region into a plurality of active regions is formed on a p-type semiconductor substrate 101, and then, in the process step of FIG. 7B, impurity injection for adjusting threshold and impurity injection for forming a well are performed to form a p-type well 104, i.e., an active region for an n-channel MISFET (NMISFET formation region Rnt) and an n-type well 105, i.e., an active region for a p-channel MISFET (PMISFET formation region Rpt).
Next, in the process step of FIG. 7C, a gate insulating film 106 is formed on each of the wells 104 and 105 and a polysilicon film 107 is deposited over the gate insulating film 106. Thereafter, a resist film 108 covering the PMISFET formation region Rpt is formed, and then, using the resist film 108 as a mask, ions of phosphorus (P+), i.e., an n-type impurity are implanted into part of the polysilicon film 107 located in the NMISFET formation region Rnt.
Moreover, in the process step of FIG. 7D, using a resist film 109 covering the NMISFET formation region Rnt as a mask, ions of boron (B+), i.e., a p-type impurity are implanted into part of the polysilicon film 107 located in the PMISFET formation region Rpt.
Next, in the process step of FIG. 7E, the polysilicon film 107 is patterned to form a gate electrode 110 of an n-channel MISFET and a gate electrode 111 of a p-channel MISFET. Note that in this case, the gate insulating film 106 may be left as it is or patterned so as to have the same shape as that of the gate electrodes 110 and 111, as shown in FIG. 7E.
Next, in the process step of FIG. 7F, using the resist film 112 covering the NMISFET formation region Rnt and the gate electrode 111 as masks, boron fluoride ions (BF2+) are implanted into the n-type well 105 to form a lightly doped impurity region 113 to serve as an LDD region or an extension region of the PMISFET.
Next, in the process step of FIG. 8A, using a resist film 114 covering the PMISFET formation region Rpt and the gate electrode 110 as masks, phosphorus ions (P+) are implanted into the p-type well 104 to form a lightly doped impurity region 115 to serve as an LDD region or an extension region of the NMISFET.
Next, in the process step of FIG. 8B, an insulating film such as a silicon oxide film and a silicon nitride film is deposited over the substrate, and then the insulating film is etched back to form a sidewall 116 covering each of side surfaces of the respective gate electrodes 110 and 111 of the MISFETs.
Next, in the process step of FIG. 8C, using the resist film 117 covering the NMISFET formation region Rnt, the gate electrode 111 and the sidewall 116 as masks, boron fluoride ions (BF2+) are implanted into the n-type well 105 to form a heavily doped impurity region 118 to serve as a source/drain region of the PMISFET.
Next, in the process step of FIG. 8D, using the resist film 119 covering the PMISFET formation region Rpt, the gate electrode 110 and the sidewall 116 as masks, arsenic ions (As+) are implanted into the p-type well 104 to form a heavily doped impurity region 120 to serve as a source/drain region of the NMISFET.
Thereafter, in the process step of FIG. 8E, RTA (thermal treatment at high temperature for a short time) for activating impurities (dopants) implanted into the gate electrodes 110 and 111 and the impurity doped regions 113, 115, 118 and 120. In this case, thermal treatment is performed, for example, at a temperature of about 1050° C. for about 10 seconds.